1. Field of the Invention
The present invention relates to delay locked loops used to provide accurate synchronization in a system operating in synchronization with a clock, semiconductor devices including the delay locked loops, and control methods for systems operating in synchronization with a clock.
2. Description of the Background Art
A case is considered in which in a system operating in synchronization with a clock a component receives a read instruction in synchronization with a clock that instructs reading data and in response to the instruction the read data is returned to a system bus in synchronization with a clock. Note that hereinafter a reference character ADR denotes a binary code, a reference character ADR less than k greater than  means a k-th bit in a binary code, referred to as a register value ADR less than k greater than  or a binary code ADR less than k greater than .
It is also assumed that with a system clock period represented by xe2x80x9cTxe2x80x9d the component requires a time period T0 to prepare read data after it has received the read instruction, and that clock period T may be greater in length than period T0 or vice versa and for an integer N there is established a relationship Nxc3x97T less than T0 less than (N+1)xc3x97T. In this scenario, the following manner is considered to provide an output.
With reference to FIG. 17, at time t1 (a rising edge 0 of a clock CLKext) a read instruction to read data is issued in synchronization with clock CLKext, and read data is prepared, and in synchronization with a subsequent rising edge 1 of clock CLKext (at time t2: t2=t1+T) the data is output.
The component requires a time period Td after it has received clock CLKext and before it outputs prepared data to an output buffer. As such, the data is actually output when time period Td elapses following the clock edge 1.
Time period Td includes, as shown in FIG. 18, a time period Tin and a time period Tout (Td=Tin+Tout). Time period Tin is required for the component to internally generate from clock CLKext a clock CLKin driving the output buffer. Time period Tout is required for driving a system bus corresponding to an output load after clock CLKin has driven and thus started the output buffer to operate until the system bus exceeds a predetermined logical threshold value.
As such, in this system it is not until Td elapses following clock edge 1 that data is actually output to a system bus. Accordingly, the system is designed to take data in at subsequent clock edge 2.
If in such an operation, system clock period T is equal to or smaller than Td and thus has a high frequency, then a problem occurs, as shown in FIG. 19. In FIG. 19, at clock edge 1 a data output operation is started, and at clock edge 2 data is not yet transmitted on a bus, since delay time Td is greater than T. As such, it is not until a subsequent clock edge 3 arrives that the system can take data in. In other words, if the system is designed to take data in at clock edge 2 the system would operate erroneously.
In particular, a recently developed memory, DDR-SDRAM (double data rate, synchronous dynamic random access memory) outputs data at both of rising edge and trailing edge of a clock. As such, if the aforementioned method of outputting data is applied to the DDR-SDRAM, as shown in FIG. 20, the same problem as described above would come to the surface at a time point when half the clock period is substantially equal to Td.
Such a disadvantage as above is conventionally overcome by a delay locked loop (hereinafter referred to as a DLL). With reference to FIG. 21, a component employing a DLL receives a system clock CLKext and internally delays the clock via a delay element by Tdll1. Then it generates an internal clock CLKin2 rising before a rising edge of the system clock by a time period corresponding to an output buffer drive time (Toutxe2x80x2=Tout).
Using internal clock CLKin2 to drive the output buffer allows read data to have been output on a bus at an edge of system clock CLKext. That is, a relation Tdll1+Toutxe2x80x2=mxc3x97T, wherein m is an integer equal to or larger than one, can be established.
Thus a DLL can be used to time an output in synchronization with a clock. The DLL can also be similarly used for an input buffer allowing a component to take in various control signals and input data through a system bus.
The operating timing of an input buffer which does not use a DLL will be described with reference to FIG. 22. As shown in FIG. 22, this input buffer without DLL requires a time period Tin after clock CLKext is received and before a component internally generates internal clock CLKin.
As such, an externally received control signal SIG is internally delayed by a time period Tinxe2x80x3 corresponding to Tin, to be a signal SIGin. At the edge timing of internal clock CLKin, signal SIGin is latched by a latch circuit 910 and ascertained. In the figure an ascertained control signal is shown.
With reference to FIG. 23, latch circuit 910 includes inverters IV1-IV4 and NAND circuits N1-N4. Inverters IV1 and IV3 operate in response to internal clock CLKin and a clock/CLKin, an inverted version of internal clock CLKin.
As such, if a DLL is not used, it is not until a delay of at least Tin elapses following an edge of system clock CLKext that a component can use a control signal. As such, the component itself would not be suitable for high speed operation.
Such delay is compensated for by the aforementioned DLL. Reference will now be made to FIG. 24 to describe an operating waveform when the DLL is used. With reference to FIG. 24, system clock CLKext is delayed in a component via a delay element by Tdll2 to generate an internal clock CLKin3 having an edge at the same position at that of a system clock CLKext. If internal clock CLKin3 is used to latch control signal SIG then control signal SIG can be latched faster than the above case by a time period corresponding to Tin. Thus the system can be designed to be suitable for high speed operation. Herein, from the above description there can be established a relationship Tdll12=mxc3x97T.
Reference will now be made to FIG. 25 to describe by way of example a configuration of a circuit configuring a DLL conventionally used. A conventional DLL 9000, as shown in FIG. 25, includes a clock buffer 1, a fine delay element 3, a coarse delay element 5, a decoder 70, a binary counter 80 corresponding to a delay register, a phase comparator 9, a timing clock generator 10, a pulse generator 11 and a replica circuit 13.
External clock CLKext is input to clock buffer 1. Clock buffer 1 outputs a clock BUFFCLK. Between external clock CLKext and clock BUFFCLK time Tin elapses.
Clock BUFFCLK is input to fine delay element 3. Fine delay element 3 delays clock BUFFCLK by Tfine to output a clock CLKA. Delay time Tfine, elapsing between clock BUFFCLK and clock CLKA, is variable, varying in a small unit Tf (a unit of approximately 40 psec) depending on the value of a 3-bit register value ADR less than 0:2 greater than  input to fine delay element 3.
Clock CLKA is input to coarse delay element 5. Coarse delay element 5 delays clock CLKA by Tcoarse to output a clock CLKB. Delay time Tcoarse, elapsing between clocks CLKA and CLKB, is variable, varying in a coarse unit Tc depending on a 6-bit register value ADR less than 3:8 greater than . It should be noted that Tc is set to be 8 times Tf in length.
Fine delay element 3 and coarse delay element 5 each provide an amount of delay determined by a register value output from binary counter 80.
In the circuit configuration, at least a delay time Tx is required for a clock to pass through fine delay element 3 and coarse delay element 5. With the clock passing through fine delay element 3 and coarse delay element 5, a delay of Tx would be inevitably result even if a register value is the value of a minimal delay time.
The conventional DLL has fine delay element 3 and coarse delay element 5 each having a delay time set by a binary code. For example, fine delay element 3 has delay periods of time Tf, 2xc3x97Tf and 3xc3x97Tf for register values ADR less than 0:2 greater than  of xe2x80x9c001xe2x80x9d, xe2x80x9c010xe2x80x9d, and xe2x80x9c011xe2x80x9d, respectively, and coarse delay element 5 has delay periods of time 7xc3x97Tc and 8xc3x97Tc for register values ADR less than 3:8 greater than  of xe2x80x9c000111xe2x80x9d and xe2x80x9c001000xe2x80x9d, respectively.
As such, if delay time Tx resulting from the aforementioned circuit configuration is also considered, then for a register value of xe2x80x9c001001xe2x80x9d determining Tcoarse and that of xe2x80x9c011xe2x80x9d determining Tfine a total of delay time Tfine+Tcoarse=Tx+3xc3x97Tf+9xc3x97Tc elapses between docks BUFFCLK and CLKB.
Hereinafter, if coarse delay element 5 receives a register value xe2x80x9c001001xe2x80x9d and fine delay element 3 receives a register value xe2x80x9c011xe2x80x9d they will be generally represented as a register value xe2x80x9c001001011xe2x80x9d.
Clock CLKB is input to pulse generator 11 generating internal clock CLKin2 used to drive an output buffer and internal clock CLKin3 used to drive an input buffer, and to replica circuit 13. Internal clock CLKin2 serves as has been described with reference to FIG. 21. Thus at the rising edge of external clock CLKext an output of the output buffer is transmitted onto a system bus.
Replica circuit 13 delays clock CLKB by a fixed delay period of time (Tinxe2x80x2+Toutxe2x80x2) imitating a sum of input buffer delay time Tin and output buffer drive time Tout, to generate a clock FBCLK (FIG. 26).
Thus between clocks BUFFCLK and FBCLK there elapses a delay period of time Tfine+Tcoarse+Tinxe2x80x2+Toutxe2x80x2. Between the issuance of external clock CLKext and the generation of clock FBCLK various signals have a relationship therebetween, as shown in FIG. 26.
Reference will now be made to FIG. 27 to describe a waveform when a DLL operates to satisfy a desired delay time. In the FIG. 27 example, clocks BUFFCLK and FBCLK rise simultaneously. External clock CLKext is ahead of clock BUFFCLK by Tin and internal clock CLKin2 has a rising edge ahead of clock FBCLK by Tinxe2x80x2+Toutxe2x80x2). Thus, internal clock CLKin2 has a rising edge ahead of that of external clock CLKext by Toutxe2x80x2. This corresponds to the timing as has been described with reference to FIG. 21. Herein replica circuit 13 provides a delay time designed so that Tin=Tinxe2x80x2 and Tout=Toutxe2x80x2.
Herein to determine the DLL""s optimal delay time a circuit is required to detect which one of clocks BUFFCLK and FBCLK rises ahead of the other. This circuit is phase comparator 9 shown in FIG. 25. Phase comparator 9 detects a phase difference between clocks BUFFCLK and FBCLK and outputs signals UPF and DNF.
Reference will now be made to FIGS. 28A and 28B to describe signals UPF and DNF. If clock FBCLK phase is ahead of clock BUFFCLK phase, phase comparator 9 provides an output xe2x80x9cupxe2x80x9d (UPF is high and DNF is low), as shown in FIG. 28A. If clock FBCLK phase is behind clock BUFFCLK phase, phase comparator 9 provides an output xe2x80x9cdownxe2x80x9d (DNF is high and UPF is low), as shown in FIG. 28B.
An exemplary configuration of phase comparator 9 is shown in FIG. 30. Phase comparator 9, as shown in FIG. 30, includes NAND circuits N5-N10. Clocks BUFFCLK and FBCLK input to NAND circuits N5 and N6, respectively, contribute to signals UPF and DNF, respectively, output from NAND circuits N9 and N10, respectively.
With reference to FIG. 25, timing clock generator 10 receives signals UPF and DNF and generates a counter updating clock CLKCNT and up and down signals UP and DN.
In response to counter updating clock CLKCNT binary counter 80 outputs register values ADR less than 0:2 greater than  and ADR less than 3:8 greater than  depending on up and down signals UP and DN.
If phase comparator 9 provides output xe2x80x9cUPxe2x80x9d then the current register value increases. For example xe2x80x9c000000010xe2x80x9d increases to xe2x80x9c000000011xe2x80x9d. If phase comparator 9 provides output xe2x80x9cDOWNxe2x80x9d then the current register value decreases. For example xe2x80x9c000000011xe2x80x9d decreases to xe2x80x9c000000010xe2x80x9d.
Decoder 70 decodes register value ADR less than 3:8 greater than . Decoder 70, as shown in FIG. 29, includes AND circuits 90#0-90#7 and 91#0-91#15.
AND circuit 90#0 receives binary code /ADR less than 0 greater than , an inverted version of binary code ADR less than 0 greater than , and binary code /ADR less than 1 greater than , an inverted version of binary code ADR less than 1 greater than , and AND circuit 90#1 receives binary codes ADR less than 0 greater than and /ADR less than 1 greater than .
AND circuit 90#2 receives binary codes /ADR less than 0 greater than  and ADR less than 1 greater than  and AND circuit 90#3 receives binary codes ADR less than 0 greater than  and ADR less than 1 greater than .
AND circuit 90#4 receives binary code /ADR less than 2 greater than , an inverted version of binary code ADR less than 2 greater than , and binary code /ADR less than 3 greater than , an inverted version of binary code ADR less than 3 greater than , and AND circuit 90#5 receives binary codes ADR less than 2 greater than and /ADR less than 3 greater than .
AND circuit 90#6 receives binary codes /ADR less than 2 greater than  and ADR less than 3 greater than  and AND circuit 90#7 receives binary codes ADR less than 2 greater than  and ADR less than 3 greater than .
AND circuit 91#i has inputs receiving an output X less than i greater than  from AND circuit 90#i and an output X less than 4 greater than  from AND circuit 90#4, wherein i=0 to 3. AND circuit 91#i+4 receives an output X less than i greater than  from AND circuit 90#i and an output X less than 5 greater than  from AND circuit 90#5, wherein i=0 to 3. AND circuit 91i+8 has inputs receiving an output X less than i greater than  from AND circuit 90#i and an output X less than 6 greater than  from AND circuit 90#6, wherein i=0 to 3. AND circuit 91#i+12 receives an output X less than i greater than  from AND circuit 90#i and an output X less than 7 greater than  from AND circuit 90#7, wherein i=0 to 3. Depending on the output from AND circuit 90#k the number of delay stages of coarse delay element 5 (k, for example) is determined, wherein k=0 to 15. While herein a 4-bit binary decoder is exemplified, those skilled in the art would readily understand that a 6-bit binary decoder receiving ADR less than 3 greater than -ADR less than 8 greater than  can also be implemented by employing a similar circuit.
If the external clock is delayed too significantly then output xe2x80x9cDOWNxe2x80x9d renders a delay time shorter and if a delay is insufficient then output xe2x80x9cUPxe2x80x9d renders a delay time longer. As a result, DLL 9000 is stabilized with a delay time as described.
Thus while detecting which one of clocks BUFFCLK and FBCLK phases is ahead of the other, the DLL appropriately adjusts the delay time of delay element 3 and that of delay element 5 to maintain clocks BUFFCLK and FBCLK rising simultaneously.
If there is a distinct phase difference, as shown in FIGS. 28A and 28B, then there would not be any problems. However, as has been described above, DLL 9000 must monitor the phase difference between clocks BUFFCLK and FBCLK and operate to adjust delay elements 3 and 5 to maintain the clocks free of any substantial phase difference.
As such, in the normal state with DLL 9000 operating, inherently there is no substantial phase difference between clocks BUFFCLK and FBCLK. In this case, the situation occurs with a certain probability in which phase comparator 9 requires a significantly long period of time to determine whether to provide output xe2x80x9cUPxe2x80x9d or xe2x80x9cDOWNxe2x80x9d.
This generally applies to flip-flops including phase comparator 9 and it is a phenomenon known as the metastable state.
However, as described in Design of CMOS Ultra LSI, BAIFUKAN, 1989, p.128, it is practically impossible to completely eliminate the possibility of occurrence of the metastable state. In such a case, using binary counter 80 as conventional may result in erroneous operation.
For example, if the current register value is xe2x80x9c011111111xe2x80x9d then the subsequent register value would be xe2x80x9c100000000xe2x80x9d for output xe2x80x9cUPxe2x80x9d and xe2x80x9c011111110xe2x80x9d for output xe2x80x9cDOWNxe2x80x9d.
More specifically in this example the MSB bit through a bit immediately preceding the LSB bit for a total of eight bits vary depending on whether phase comparator 9 outputs xe2x80x9cUPxe2x80x9d or xe2x80x9cDOWNxe2x80x9d. In other words, for xe2x80x9cUPxe2x80x9d nine bits have carry xe2x80x9c1xe2x80x9d, whereas for xe2x80x9cDOWNxe2x80x9d the bits other than the LSB bit have carry xe2x80x9c0xe2x80x9d. Thus a carry has a value significantly varying depending on whether phase comparator 9 outputs xe2x80x9cUPxe2x80x9d or xe2x80x9cDOWNxe2x80x9d.
In such an instant if the metastable state occurs it is not certain whether phase comparator 9 is xe2x80x9cUPxe2x80x9d or xe2x80x9cDOWNxe2x80x9d, i.e., whether a register""s carry is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. As a result, a subsequent register state is not ascertained. In effect, it has a random value.
In other words, the DLL would have a delay time suddenly varying from a value to a significantly different value. For example, if a register value xe2x80x9c011111111xe2x80x9d changes to xe2x80x9c010101010xe2x80x9d then the delay elements would have a delay time Tcoarse+Tfine changing from 31xc3x97Tc+7xc3x97Tf to 21xc3x97Tc+2xc3x97Tf.
Thus, in the DLL, expected to be stable in a desired delay state, a delay time suddenly and significantly diverges, resulting in the entire system operating erroneously.
An object of the present invention is to provide a configuration capable of minimizing skipping of delay when a clock is generated, and a method thereof.
According to one aspect of the present invention, a delay locked loop includes a delay circuit delaying a first clock to output a second clock, a detector detecting a phase difference between the first and second clocks, and a gray code counter using a gray cord, responsive to an output of the detector for generating a signal adjusting an amount of delay of the delay circuit.
Preferably the gray code counter includes a gray code register storing the gray code, a binary code converter converting the gray code into a binary code, an upward carry/downward carry generator using the binary code stored in the binary code converter, to generate an upward carry signal and a downward carry signal, and a carry multiplexer generating from the upward carry signal and the downward carry signal a carry signal corresponding to a result obtained by the detector, for updating the gray code in the gray code register.
In particular the delay circuit includes a fine delay element and a coarse delay element having an amount of delay greater per unit than the fine delay element, the fine delay element having an amount of delay adjusted by the binary code stored in the binary code converter, the coarse delay element having an amount of delay adjusted by the gray code stored in the gray code register.
According to another aspect of the present invention, a semiconductor device including a delay locked loop includes an input buffer receiving an external clock and outputting a first internal clock, a delay circuit delaying the first internal clock to output a second internal clock, a detector detecting a phase difference between the first and second internal clocks, and a gray code counter using a gray code, responsive to an output of the detector for generating a signal adjusting an amount of delay of the delay circuit.
Preferably the gray code counter includes a gray code register storing the gray code, a binary code converter converting the gray code into a binary code, an upward carry/downward carry generator using the binary code stored in the binary code converter, to generate an upward carry signal and a downward carry signal, and a carry multiplexer generating from the upward carry signal and the downward carry signal a carry signal corresponding to a result obtained by the detector, for updating the gray code in the gray code register.
In particular the delay circuit includes a fine delay element and a coarse delay element having an amount of delay greater per unit than the fine delay element, the fine delay element having an amount of delay adjusted by the binary code stored in the binary code converter, the coarse delay element having an amount of delay adjusted by the gray code stored in the gray code register.
Preferably the semiconductor device further includes an input circuit operative in response to the second internal clock for externally receiving a signal or an output circuit operative in response to the second internal clock for externally outputting a signal. In particular the semiconductor device further includes a memory array having a plurality of memory cells, and the output circuit receives a signal for writing/reading data to/from the memory cell array and the output circuit externally outputs data read from the memory cell array.
According to still another aspect of the present invention, a semiconductor device including a delay locked loop includes a first input buffer receiving at least a first external clock and a second external clock complementary in phase to the first external clock, and outputting a first internal clock at the timing of the rising edge of the first external clock when a potential of the first external clock is equal to that of the second external clock, a second input buffer receiving at least the first and second external clocks, and outputting a second internal clock at the timing of the rising edge of the second external clock when a potential of the first external clock is equal to that of the second external clock, a first delay circuit delaying the first internal clock to output a third internal clock, a second delay circuit delaying the second internal clock to output a fourth internal clock, a detector detecting a phase difference between the first and third internal clocks, and a gray code counter using a gray code, responsive to an output of the detector for generating a signal adjusting an amount of delay of the first delay circuit and an amount of delay of the second delay circuit.
Preferably the semiconductor device also includes an output circuit operative in response to the third and fourth internal clocks for externally outputting a signal.
In particular the semiconductor device further includes a memory cell array having a plurality of memory cells, wherein the output circuit is responsive to the third and fourth internal clocks for externally outputting data read from the memory cell array.
According to still another aspect of the present invention, a control method for a system operating in synchronization with a clock, includes the steps of inputting an external clock to an input buffer to generate a first internal clock therefrom, delaying the first internal clock to output a second internal clock, detecting a phase difference between the first and second internal clocks, and using a gray code to determine an amount of delay to be applied in the step of delaying, the amount of delay corresponding to a result obtained in the step of detecting.
Preferably the step of using the gray code includes the steps of converting the gray code into a binary code, using the binary code to generate an upward carry signal and a downward carry signal, and referring to a result obtained in the step of detecting, to generate a carry signal from the upward carry signal and the downward carry signal for updating the gray code.
In particular the present method further includes the step of externally outputting data in response to the second internal clock. Furthermore the present method also includes the step of externally receiving data in response to the second internal clock.
Thus the present DLL circuit employs a gray code counter as a delay register adjusting an amount of delay. This can prevent a carry from arising at more than one bit. Thus the DLL can have a delay value stabilized to minimize skipping of a delay to achieve reliable, rapid operation.
Furthermore the present invention can provide a semiconductor device including a DLL circuit employing a gray code counter as a delay register adjusting an amount of delay when an external clock is delayed to generate an internal clock. Thus skipping of delay can in principle be minimized. As such, using the internal clock to control input and output buffers can provide reliable, rapid operation.
Furthermore the present invention can provide a control method for a system operating in synchronization with a clock, employing a gray code to control an amount of delay to in principle minimize a skipping of delay. Thus data input can be timed in stable manner when it is input. Similarly, data output can be stable.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.